Computer systems typically have a processor core that utilizes a cache for fast data retrieval and storage. When a processor core requests a block of memory from an I/O controller to store in the cache, the computer system may perform direct memory access (DMA) write operations to store the data in the cache. When the cache already has a copy of data corresponding to the cache line, the cache invalidates its copy in order to receive new cache line data. In turn, the I/O controller provides new cache line data to a memory controller, which stores the new cache line data in memory and also provides the new cache line data to the cache. At times, the I/O controller may have a partial line of cache data (e.g, lower order bytes). In this situation, the memory controller merges partial write data with existing cache line data and provides the merged cache line to the cache.